US 12,396,202 B2
Vertical fin field effect transistor, vertical fin field effect transistor arrangement, and method for forming a vertical fin field effect transistor
Daniel Krebs, Aufhausen (DE); Joachim Rudhard, Leinfelden-Echterdingen (DE); Alberto Martinez-Limia, Tuebingen (DE); Jens Baringhaus, Sindelfingen (DE); and Wolfgang Feiler, Reutlingen (DE)
Assigned to ROBERT BOSCH GMBH, Stuttgart (DE)
Appl. No. 17/788,653
Filed by Robert Bosch GmbH, Stuttgart (DE)
PCT Filed Feb. 15, 2021, PCT No. PCT/EP2021/053596
§ 371(c)(1), (2) Date Jan. 5, 2023,
PCT Pub. No. WO2021/165183, PCT Pub. Date Aug. 26, 2021.
Claims priority of application No. 10 2020 202 038 (DE), filed on Feb. 18, 2020.
Prior Publication US 2023/0118158 A1, Apr. 20, 2023
Int. Cl. H01L 21/78 (2006.01); H01L 29/08 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/62 (2025.01) [H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 84/853 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A vertical fin field-effect transistor, comprising:
a semiconductor fin;
an n-doped source region;
an n-doped drift region;
an n-doped channel region in the semiconductor fin, situated vertically between the source region and the drift region;
at least one gate region horizontally adjacent to the channel region;
a gate dielectric that electrically insulates the gate region from the channel region, a boundary surface between the gate dielectric and the channel region and/or the gate dielectric having negative boundary surface charges;
a p-doped gate shielding region that is situated below the gate region in such a way that, in a vertical projection, the gate shielding region lies at least partly within a surface limited by the gate dielectric;
a source contact that is connected in electrically conductive fashion to the source region; and
an electrically conductive region between the gate region and the p-doped gate shielding region;
wherein the p-doped gate shielding region is connected in electrically conductive fashion to the source contact by the electrically conductive region.