| CPC H10D 30/475 (2025.01) [H10D 62/8503 (2025.01)] | 16 Claims |

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1. A semiconductor device comprising:
a channel layer;
a barrier layer disposed above the channel layer;
a protective layer disposed on the barrier layer; and
an insulating layer disposed on the protective layer, wherein
a composition of the barrier layer is represented by Inx1Alx2Ga1-x1-x2N, where 0.00<=x1<=0.20, and 0.10<=x2<=1.00,
a composition of the protective layer is represented by Iny1Aly2Ga1-y1-y2N, where 0.00<=y1<=0.20, and 0.10<=y2<=1.00, x2<y2, and
the protective layer is an amorphous layer.
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