US 12,396,193 B2
Semiconductor structure and preparation method therefor
Kai Cheng, Suzhou (CN)
Assigned to ENKRIS SEMICONDUCTOR, INC., Suzhou (CN)
Filed by ENKRIS SEMICONDUCTOR, INC., Suzhou (CN)
Filed on Oct. 26, 2021, as Appl. No. 17/510,558.
Application 17/510,558 is a continuation of application No. PCT/CN2019/084603, filed on Apr. 26, 2019.
Prior Publication US 2022/0052191 A1, Feb. 17, 2022
Int. Cl. H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/47 (2025.01) [H10D 30/015 (2025.01); H10D 62/8503 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a channel layer and a barrier layer sequentially disposed on the substrate; and
a gate structure disposed on the barrier layer, wherein the gate structure comprises a p-type semiconductor layer disposed on the barrier layer, an n-type semiconductor layer disposed on the p-type semiconductor layer, a gate disposed on the n-type semiconductor layer, and a cap layer located between the p-type semiconductor layer and the barrier layer, the gate penetrates the n-type semiconductor layer, and a bottom of the gate is in contact with the p-type semiconductor layer; the semiconductor structure further comprises a source and a drain, wherein the source and the drain are respectively disposed on two sides of the gate structure; the cap layer is GaN; a side surface, facing the source, of the p-type semiconductor layer, a side surface, facing the source, of the n-type semiconductor layer, a side surface, facing the source, of the gate and a side surface, facing the source, of the cap layer are located in a same first plane, a side surface, facing the drain, of the p-type semiconductor layer, a side surface, facing the drain, of the n-type semiconductor layer, a side surface, facing the drain, of the gate and a side surface, facing the drain, of the cap layer are located in a same second plane, an entire top surfaces of the n-type semiconductor layer is covered by the gate, and an entire top surfaces of the p-type semiconductor layer is covered by the n-type semiconductor layer and the gate; the cap layer is completely covered by the p-type semiconductor layer, the n-type semiconductor layer and the gate; and there is a gap, between the first plane and a plane, facing the gate, of the source, exposing a part of a top surface of the barrier layer, and there is a gap, between the second plane and a plane, facing the gate, of the drain, exposing a part of the top surface of the barrier layer.