US 12,396,191 B2
Isolation structures of semiconductor devices
Jia-Chuan You, Dayuan Township (TW); Li-Yang Chuang, Hsinchu (TW); Chih-Hao Wang, Baoshan Township (TW); Shi Ning Ju, Hsinchu (TW); and Kuo-Cheng Chiang, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd.
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,953.
Application 18/447,953 is a division of application No. 17/666,241, filed on Feb. 7, 2022, granted, now 12,051,738.
Application 17/666,241 is a continuation of application No. 16/776,540, filed on Jan. 30, 2020, granted, now 11,245,028, issued on Feb. 8, 2022.
Prior Publication US 2023/0387268 A1, Nov. 30, 2023
Int. Cl. H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/822 (2025.01); H10D 84/83 (2025.01)
CPC H10D 30/024 (2025.01) [H10D 62/115 (2025.01); H10D 62/822 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first vertical structure and a second vertical structure on a substrate;
an isolation layer surrounding the first and second vertical structures;
an isolation structure on the isolation layer and between the first and second vertical structures, wherein a bottom portion of the isolation structure is embedded in the isolation layer and a top portion of the isolation structure comprises a footing region with sidewalls tapered from a bottom portion of the footing region to a top portion of the footing region; and
a gate structure comprising a first portion on the first vertical structure and a second portion on the second vertical structure, wherein the isolation structure is interposed between the first and second portions of the gate structure, and wherein the footing region is below a top surface of the gate structure.