US 12,396,186 B2
Method of making semiconductor device including metal insulator metal capacitor
Yan-Jhih Huang, Hsinchu (TW); Chun-Yuan Hsu, Hsinchu (TW); Chien-Chung Chen, Hsinchu (TW); and Yung-Hsieh Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 29, 2023, as Appl. No. 18/522,752.
Application 18/522,752 is a division of application No. 17/534,431, filed on Nov. 23, 2021, granted, now 11,855,126.
Application 16/780,686 is a division of application No. 14/103,651, filed on Dec. 11, 2013, granted, now 10,553,672, issued on Feb. 4, 2020.
Application 17/534,431 is a continuation of application No. 16/780,686, filed on Feb. 3, 2020, granted, now 11,201,206, issued on Dec. 14, 2021.
Prior Publication US 2024/0096929 A1, Mar. 21, 2024
Int. Cl. H10D 1/68 (2025.01); H01L 23/522 (2006.01); H10D 1/00 (2025.01); H10B 41/30 (2023.01); H10D 64/01 (2025.01); H10D 89/10 (2025.01)
CPC H10D 1/692 (2025.01) [H01L 23/5223 (2013.01); H10D 1/042 (2025.01); H10D 1/714 (2025.01); H01L 23/5222 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01); H10B 41/30 (2023.02); H10D 1/68 (2025.01); H10D 64/035 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, the method comprising:
forming a circuit layer over a substrate;
depositing an insulator over the substrate;
patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench exposes a portion of the substrate exposed by the circuit layer;
filling the test line trench to define a test line electrically connected to the circuit layer; and
filling the first trench and the second trench to define a capacitor.