US 12,396,184 B2
Semiconductor devices including resistor structures
Tae-yeol Kim, Hwaseong-si (KR); Hyon-wook Ra, Hwaseong-si (KR); Seo-bum Lee, Seoul (KR); Jun-soo Kim, Uijeongbu-si (KR); and Chung-hwan Shin, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 21, 2023, as Appl. No. 18/371,328.
Application 18/371,328 is a continuation of application No. 17/118,078, filed on Dec. 10, 2020, granted, now 11,804,516.
Application 17/118,078 is a continuation of application No. 15/862,774, filed on Jan. 5, 2018, granted, now 10,886,361, issued on Jan. 5, 2021.
Claims priority of application No. 10-2017-0080734 (KR), filed on Jun. 26, 2017.
Prior Publication US 2024/0014250 A1, Jan. 11, 2024
Int. Cl. H10D 1/47 (2025.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 84/40 (2025.01); H10D 84/80 (2025.01); H01L 21/285 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01); H10D 30/69 (2025.01); H10D 64/68 (2025.01)
CPC H10D 1/47 (2025.01) [H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 23/5228 (2013.01); H01L 23/5283 (2013.01); H10D 84/403 (2025.01); H10D 84/817 (2025.01); H01L 21/28518 (2013.01); H01L 21/76834 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/53223 (2013.01); H01L 23/5329 (2013.01); H10D 30/795 (2025.01); H10D 64/691 (2025.01); H10D 84/811 (2025.01)] 20 Claims
OG exemplary drawing
 
11. A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate including a first region and a second region;
forming an active region disposed on the first region and the second region of the substrate;
forming a lower structure on the first region and the second region of the substrate, the lower structure including a gate structure and a lower interlayer insulating layer that contacts a side wall of the gate structure;
forming a resistor structure on the lower structure on the second region of the substrate, the resistor structure including a first insulating layer, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer;
forming a resistor contact hole penetrating the second insulating layer and the resistor layer; and
forming a resistor contact filling the resistor contact hole, the resistor contact directly contacts the first insulating layer,
wherein the forming the resistor contact hole includes:
performing a first etching process to pattern the second insulating layer and the first insulating layer; and
performing a second etching process of etching the resistor layer using the second insulating layer as an etch mask and the first insulating layer using the resistor layer as an etch mask, and
wherein in the second etching process, a tilt angle of a side wall of the resistor contact hole with respect to a vertical direction perpendicular to an upper surface of the substrate is changed where the resistor contact hole penetrates the resistor layer and where the resistor contact hole penetrates the first insulating layer.