| CPC H10D 1/20 (2025.01) [H01L 23/5227 (2013.01); H05K 1/16 (2013.01); H10B 12/50 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a plurality of pads connected to an external device and each configured to receive a signal from the external device;
a memory cell array including a plurality of memory cells;
a logic circuit configured to control the memory cell array and including an internal circuit and a plurality of input/output circuits connected to the plurality of pads; and
an inductor circuit connected between a first pad of the plurality of pads and a first input/output circuit of the plurality of input/output circuits in series, wherein:
the inductor circuit includes an inductor pattern connected between the first pad and the first input/output circuit, and a variable pattern disposed between at least portions of the inductor pattern,
the variable pattern is separated from the inductor pattern, the first pad, and the first input/output circuit, and
the first input/output circuit connected to the inductor circuit is configured to receive the signal through the inductor circuit and to transmit the signal to the internal circuit.
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13. A semiconductor device, comprising:
a semiconductor substrate;
a plurality of elements disposed on the semiconductor substrate; and
an interconnection region having a plurality of wiring patterns connected to the plurality of elements, the plurality of wiring patterns including an inductor pattern connected to one of a plurality of pads and a variable pattern disposed on a same layer as the inductor pattern, wherein:
the inductor pattern includes a first line and a second line adjacent to both sides of the variable pattern in a first direction, parallel to an upper surface of the semiconductor substrate,
the first line, the second line, and the variable pattern extend in a second direction, intersecting the first direction, and parallel to the upper surface of the semiconductor substrate,
the first line and the second line are connected to each other, and
the variable pattern is disposed between the first line and the second line in the first direction.
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18. A semiconductor device, comprising:
a plurality of pads connected to an external device and each configured to receive a signal from the external device;
an input/output circuit configured to receive the signal from a first pad of the plurality of pads; and
an inductor circuit connected between the first pad and the input/output circuit in series, wherein:
the inductor circuit includes an inductor pattern connected between the first pad and the input/output circuit, and a variable pattern physically separated from the inductor pattern and adjacent to the inductor pattern, and
the inductor pattern includes a plurality of line patterns connected to each other, in which a first interval between some line patterns adjacent to each other and adjacent to the variable pattern, among the plurality of line patterns, is greater than a second interval between other portions of the line patterns adjacent to each other and not adjacent to the variable pattern.
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