US 12,396,182 B2
Capacitor and manufacturing method thereof, and semiconductor device
Mengkang Yu, Hefei (CN); Xingsong Su, Hefei (CN); and Weiping Bai, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on Nov. 14, 2022, as Appl. No. 18/054,980.
Claims priority of application No. 202111473510.7 (CN), filed on Nov. 30, 2021.
Prior Publication US 2023/0170382 A1, Jun. 1, 2023
Int. Cl. H10D 1/68 (2025.01); H10D 1/00 (2025.01)
CPC H10D 1/042 (2025.01) [H10D 1/043 (2025.01); H10D 1/716 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A method of manufacturing a capacitor, comprising:
providing a filling layer;
forming a plurality of openings on the filling layer;
separately forming a bottom electrode in each of the plurality of openings;
forming a dielectric layer on a remaining part of the filling layer and the plurality of bottom electrodes, wherein one side of the dielectric layer is in contact with the plurality of bottom electrodes and along the thickness direction of the filling layer, the length of each of the plurality of bottom electrodes is the same as that of the dielectric layer;
forming a top electrode structure on the dielectric layer, wherein the other side of the dielectric layer is in contact with the top electrode structure; and
forming a gap filling layer by using a final remaining part of the filling layer, to fill remaining gaps between the plurality of bottom electrodes.