US 12,396,180 B2
Pillar and word line plate architecture for a memory array
Lorenzo Fratin, Buccinasco (IT); Enrico Varesi, Milan (IT); Paolo Fantini, Vimercate (IT); and Thomas M. Graettinger, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 12, 2022, as Appl. No. 17/819,569.
Prior Publication US 2024/0057348 A1, Feb. 15, 2024
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/845 (2023.02) [H10N 70/066 (2023.02)] 5 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a stack comprising a plurality of first layers, each first layer comprising a respective first electrode;
a plurality of first memory material elements each located at a respective first layer of the plurality of first layers and coupled with a respective first electrode;
a plurality of second memory material elements each located at the respective first layer of the plurality of first layers and coupled with the respective first electrode; and
a pillar extending through the plurality of first layers, the pillar comprising:
a second electrode extending through the plurality of first layers and coupled with the plurality of first memory material elements;
a third electrode extending through the plurality of first layers and coupled with the plurality of second memory material elements; and
one or more dielectric materials interposed between the second electrode and the third electrode and extending through the plurality of first layers, the one or more dielectric materials electrically isolating the second electrode from the third electrode.