| CPC H10B 43/40 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a stack structure including a gate stack region and a dummy stack region, the gate stack region including interlayer insulating layers and gate electrodes alternately stacked, and the dummy stack region including dummy insulating layers and dummy horizontal layers alternately stacked;
a separation structure penetrating through the stack structure, surrounding an entire external side surface of the gate stack region, and having a shape of a closed loop;
a vertical memory structure penetrating through the gate stack region in a first region; and
gate contact structures electrically connected to the gate electrodes in a second region adjacent to the first region, wherein:
the gate electrodes include a first gate electrode and a second gate electrode disposed at a level higher than a level of the first gate electrode,
each of the gate contact structures includes a gate contact plug and a first insulating spacer surrounding a side surface of the gate contact plug,
the gate contact plugs include a first gate contact plug and a second gate contact plug,
the first gate contact plug penetrates through the second gate electrode, and contacts the first gate electrode, and
the second gate contact plug is at a higher level than the first gate electrode, and contacts the second gate electrode.
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