| CPC H10B 43/27 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H10B 43/40 (2023.02); H01L 2224/023 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a cell substrate comprising a cell array region and an extension region;
a first mold structure on the cell substrate, the first mold structure comprising a plurality of first gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region;
a second mold structure on the first mold structure, the second mold structure comprising a plurality of second gate electrodes sequentially stacked on the first mold structure on the cell array region and stacked in a stepwise manner on the extension region;
a channel structure passing through the first mold structure and the second mold structure on the cell array region; and
a cell contact structure passing through the first mold structure and the second mold structure on the extension region,
wherein the cell contact structure comprises a lower conductive pattern connected to one of the plurality of first gate electrodes, an upper conductive pattern connected to one of the plurality of second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.
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