US 12,396,171 B2
Method of fabricating three-dimensional NAND memory
Yaqin Liu, Hubei (CN); Kun Zhang, Hubei (CN); Linchun Wu, Hubei (CN); and Wenxi Zhou, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Mar. 31, 2022, as Appl. No. 17/709,668.
Claims priority of application No. 202110525974.1 (CN), filed on May 14, 2021.
Prior Publication US 2022/0367510 A1, Nov. 17, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/78 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/7806 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack on a substrate;
forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack that is farther away from the substrate;
forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening;
removing the substrate from a second side of the dielectric stack to expose a portion of the first layer located at the bottom of the first opening, wherein the second side of the dielectric stack is opposite to the first side of the dielectric stack;
removing the portion of the first layer located at the bottom of the first opening from the second side of the dielectric stack to expose a portion of the second layer; and
after removing a first semiconductor layer, forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.