US 12,396,166 B2
Semiconductor device and method for forming the wiring structures avoiding short circuit thereof
Hidenori Yamaguchi, Higashihiroshima (JP); Katsumi Koge, Higashihiroshima (JP); Junya Suzuki, Higashihiroshima (JP); and Hiroshi Ichikawa, Higashihiroshima (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 29, 2024, as Appl. No. 18/622,235.
Application 18/622,235 is a division of application No. 17/355,006, filed on Jun. 22, 2021, abandoned.
Prior Publication US 2024/0244836 A1, Jul. 18, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/50 (2023.02) [H10B 12/0335 (2023.02); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a repetition of four line-shaped mask patterns extending across a memory cell region and a peripheral region provided over a substrate;
forming a first resist pattern arranged periodically on the line-shaped mask patterns so as to sandwich three of the line-shaped mask patterns in between;
forming a second resist pattern arranged periodically on the line-shaped mask patterns so as to sandwich one of the line-shaped mask patterns between the first resist pattern and the second resist pattern; and
transferring a staggered pattern to a member arranged under the line-shaped mask patterns, the staggered pattern being formed by the line-shaped mask patterns, the first resist pattern, and the second resist pattern using the line-shaped mask patterns, the first resist pattern, and the second resist pattern as masks.