| CPC H10B 12/50 (2023.02) [H10B 12/09 (2023.02); H10B 12/315 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate including an active cell region in which a cell circuit is provided, a peripheral region in which peripheral circuits for an operation of the cell circuit provided, a boundary region between the active cell region and the peripheral region, and a dummy cell region between the active cell region and the boundary region;
a plurality of word lines on the active cell region of the substrate, the plurality of word lines being spaced apart from each other in a first direction and extending in a second direction crossing the first direction;
a plurality of bit lines on the active cell region of the substrate, the plurality of bit lines crossing the plurality of word lines, extending in the first direction and being spaced apart from each other in the second direction, the plurality of bit lines comprising a plurality of first bit lines and a plurality of second bit lines, and the plurality of first and second bit lines being alternately arranged in the second direction;
a plurality of bit line pads on the boundary region of the substrate and spaced apart from each other in the second direction, wherein the plurality of second bit lines extend on the dummy cell region and the boundary region in the first direction, and are connected to the plurality of bit line pads, respectively; and
an insulating separation pattern on the boundary region of the substrate and between two adjacent bit line pads among the plurality of bit line pads, wherein a portion of the insulating separation pattern extends into a region between two adjacent second bit lines among the plurality of second bit lines on the boundary region and is in contact with an end portion of a corresponding first bit line of the plurality of first bit lines.
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