US 12,396,161 B2
Semiconductor structure including bit line compose of a metal layer and a metal silicide layer and manufacturing method thereof
Guangsu Shao, Hefei (CN); and Deyuan Xiao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 23, 2022, as Appl. No. 17/934,703.
Claims priority of application No. 202210540685.3 (CN), filed on May 17, 2022.
Prior Publication US 2023/0413536 A1, Dec. 21, 2023
Int. Cl. H10B 12/00 (2023.01); H10D 30/67 (2025.01)
CPC H10B 12/482 (2023.02) [H10B 12/053 (2023.02); H10B 12/488 (2023.02); H10D 30/6735 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate provided with a plurality of trenches arranged at intervals;
a bit line at least located on a sidewall of the trench, wherein both the bit line and the trench extend along a first direction;
a bit line isolation layer filled in the trench;
a plurality of first semiconductor pillars arranged at intervals on a surface of the substrate;
a plurality of word lines arranged at intervals, wherein the word lines are separated from the substrate and cover the first semiconductor pillars by a certain height, the word line extends along a second direction, and the second direction is different from the first direction; and
a dielectric layer at least located between the first semiconductor pillar and the word line;
wherein the bit line comprises a metal layer and a metal silicide layer that are in contact with each other and extend along the first direction; and the metal layer is located on the sidewall of the trench, and the metal silicide layer is located in the substrate between adjacent ones of the trenches.