| CPC H10B 12/312 (2023.02) [G11C 5/063 (2013.01); H10B 12/0335 (2023.02); H10B 12/05 (2023.02)] | 10 Claims |
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1. A memory device, comprising:
a substrate;
a memory cell array disposed on the substrate and including a plurality of memory cells, wherein each of the plurality of memory cells includes:
a transistor unit including a drain region, a gate structure, and a source region that are arranged along a first direction; and
a memory unit electrically connected to the transistor unit; and
a memory cell interconnection structure disposed on the substrate and configured to establish an electrical connection between the plurality of memory cells, wherein the memory cell interconnection structure includes:
a dielectric layer directly covering the substrate and the transistor units; and
a plurality of drain conductive structures, wherein each of the plurality of drain conductive structures is electrically connected to a corresponding one of the memory units, and includes at least one drain conductive pillar, and wherein the at least one drain conductive pillar includes a first contact portion and a second contact portion that are connected to each other and embedded in the dielectric layer;
wherein the first contact portion is physically connected to the drain region of a corresponding one of the transistor units, and one side surface of the first contact portion is recessed along the first direction with respect to one side surface of the second contact portion, so as to form one stepped structure.
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