US 12,396,155 B2
Backend memory with air gaps in upper metal layers
Abhishek A. Sharma, Hillsboro, OR (US); Albert B. Chen, Portland, OR (US); Wilfred Gomes, Portland, OR (US); Fatih Hamzaoglu, Portland, OR (US); Travis W. Lajoie, Forest Grove, OR (US); Van H. Le, Beaverton, OR (US); Alekhya Nimmagadda, Hillsboro, OR (US); Miriam R. Reshotko, Portland, OR (US); and Hui Jae Yoo, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 18, 2021, as Appl. No. 17/351,301.
Prior Publication US 2022/0406782 A1, Dec. 22, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 23/528 (2006.01); H10D 62/10 (2025.01)
CPC H10B 12/30 (2023.02) [H01L 23/5283 (2013.01); H10B 12/02 (2023.02); H10D 62/115 (2025.01)] 20 Claims
OG exemplary drawing
 
14. An integrated circuit (IC) package, comprising:
an IC device; and
a further IC component, coupled to the IC device,
wherein the IC device includes:
a frontend layer with a plurality of frontend transistors, and
a metallization stack over the frontend layer, the metallization stack including:
a backend memory layer with a plurality of memory cells with backend transistors,
a layer with a plurality of conductive lines, wherein the backend memory layer is between the frontend layer and the layer with the plurality of conductive lines, and the plurality of conductive lines includes a first conductive line and a second conductive line,
an air gap between the first conductive line and the second conductive line, and
an etch-stop material at least partially at a first sidewall, a second sidewall, and a bottom of the air gap.