| CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] | 12 Claims |
|
1. A semiconductor element memory device comprising a block in which a plurality of semiconductor memory cells is arrayed in a matrix on a substrate, each of the semiconductor memory cells contained in the block in turn including:
a semiconductor base body erected on a substrate in a vertical direction of the substrate or extended on the substrate in a horizontal direction,
a first impurity region and a second impurity region provided on opposite ends of the semiconductor base body;
a gate insulating layer placed in contact with a lateral surface of the semiconductor base body between the first impurity region and the second impurity region;
a first gate conductor layer covering part or all of the gate insulating layer; and
a second gate conductor layer located adjacent to the first gate conductor layer and placed in contact with a lateral surface of the gate insulating layer,
wherein positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current are held in the semiconductor base body by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region,
a memory write operation is performed by setting a voltage of the semiconductor base body to a first data retention voltage higher than a voltage of the first impurity region and/or the second impurity region by about a built-in voltage,
a memory erase operation is performed by controlling voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer and thereby extracting the positive hole groups from one or both of the first impurity region and the second impurity region,
the voltage of the semiconductor base body is set to a second data retention voltage lower than the first data retention voltage,
in the block, the first impurity region of each of the semiconductor memory cells is connected with a source line and the second impurity region is connected alternately with an odd-numbered bit line and an even-numbered bit line and one of the first and second gate conductor layers is connected with a word line and another is connected with a first drive control line, and
in the block, using voltages applied to the source line, the bit lines, the first drive control line, and the word line, storage data of a plurality of the semiconductor base bodies selected by the word line is read alternately to the odd-numbered bit line and the even-numbered bit line.
|