US 12,396,148 B2
Method of manufacturing integrated circuit device
Minkyu Suh, Suwon-si (KR); Yangdoo Kim, Suwon-si (KR); Yonghwan Kim, Suwon-si (KR); Sangwuk Park, Suwon-si (KR); Geonyeop Lee, Suwon-si (KR); Dokeun Lee, Suwon-si (KR); and Jungpyo Hong, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 2, 2022, as Appl. No. 17/979,069.
Claims priority of application No. 10-2022-0040461 (KR), filed on Mar. 31, 2022.
Prior Publication US 2023/0320061 A1, Oct. 5, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/03 (2023.02) 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a mold structure on a substrate, such that the mold structure includes a mold layer and a support layer that are sequentially stacked in a vertical direction;
forming a vertical hole through the mold structure in the vertical direction by performing dry-etching, such that a bowing space is formed at a first vertical level area in a portion of the mold layer, the bowing space extending away from the vertical hole in a horizontal direction;
exposing an interior of the vertical hole and the bowing space to a preprocessing atmosphere, such that the support layer has a first surface state and the mold layer has a second surface state in the vertical hole, the second surface state being different from the first surface state;
forming a bowing complementary pattern in the bowing space by a selective deposition process, using a difference between the first surface state and the second surface state, such that the bowing space is filled by the bowing complementary pattern; and
forming a lower electrode in the vertical hole, such that the lower electrode is in contact with the mold layer, the support layer, and the bowing complementary pattern.