| CPC H04W 4/80 (2018.02) [H04B 17/318 (2015.01); H04L 43/022 (2013.01); H04L 43/106 (2013.01); H04L 69/22 (2013.01); H04W 28/021 (2013.01); H04W 40/244 (2013.01); G01S 11/08 (2013.01); H04W 84/18 (2013.01)] | 20 Claims |

|
1. A device comprising:
a packet detector configured to identify a data packet included in a received signal having a symbol frequency;
a time stamping unit configured to generate an initial time stamp in response to the packet detector identifying the data packet; and
one or more processors configured to:
identify an estimated timing of a symbol boundary based on a time of a change in phase of the received signal estimated by using a phase rotation speed and a sample time of an IQ sample of a plurality of IQ samples to compute the time of the change in phase, the estimated timing of the symbol boundary being a time of a data value transition between symbols, the phase rotation speed being identified by phase features of the received signal, and based on a modulation encoding scheme of the received signal; and
generate an estimated time of arrival based on the initial time stamp, the plurality of IQ samples, and the identified timing of the symbol boundary, wherein the estimated time of arrival is a corrected time of arrival.
|