US 12,395,764 B2
Solid-state imaging device with redundant ad conversion circuits and selective exclusion
Norihiko Sumitani, Osaka (JP); Hiroshi Fujinaka, Osaka (JP); Yutaka Abe, Osaka (JP); and Takayasu Kito, Osaka (JP)
Assigned to NUVOTON TECHNOLOGY CORPORATION JAPAN, Kyoto (JP)
Filed by Nuvoton Technology Corporation Japan, Kyoto (JP)
Filed on Dec. 1, 2023, as Appl. No. 18/526,611.
Application 18/526,611 is a continuation of application No. PCT/JP2022/019635, filed on May 9, 2022.
Claims priority of application No. 2021-095194 (JP), filed on Jun. 7, 2021.
Prior Publication US 2024/0163579 A1, May 16, 2024
Int. Cl. H04N 25/78 (2023.01); H04N 25/68 (2023.01); H04N 25/771 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/68 (2023.01); H04N 25/771 (2023.01)] 10 Claims
OG exemplary drawing
 
1. A solid-state imaging device comprising:
a plurality of pixel circuits arranged in rows and columns;
a plurality of selectors that each receive, as inputs, two pixel signals corresponding to two columns different from each other;
k column AD conversion circuits that perform AD conversion on pixel signals output from the plurality of selectors, k being an integer greater than or equal to two; and
m column AD conversion circuits that are provided redundantly, m being an integer greater than or equal to two, wherein
the plurality of selectors selectively exclude, from among the k column AD conversion circuits and the m column AD conversion circuits, m column AD conversion circuits corresponding to m columns adjacent to each other, and associate k pixel signals output from the plurality of pixel circuits with k column AD conversion circuits which have not been excluded.