US 12,395,189 B2
Technique to perform decoding of wireless communications signal data
Jeremy David Furtek, San Antonio, TX (US)
Assigned to NVIDIA Technologies, Inc., Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Jan. 20, 2021, as Appl. No. 17/153,795.
Prior Publication US 2022/0231701 A1, Jul. 21, 2022
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/25 (2006.01)
CPC H03M 13/1165 (2013.01) [H03M 13/255 (2013.01); H03M 13/616 (2013.01); H03M 13/6312 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A processor, comprising:
one or more circuits to select one of a plurality of Fifth Generation (5G) signal decoding operations based, at least in part, on a sparsity of error correction information associated with the 5G signal, wherein the 5G signal decoding operation is a low density parity check (LDPC) decoding operation, and the one or more circuits are to select a first type of LDPC decoding operation in response to the sparsity of error correction information is less than or equal to a predefined threshold value, and are to select a second type of LDPC decoding operation in response to the sparsity of error correction information is greater than the predefined threshold value, where the error correction information is represented using a quasi-cyclic LDPC (QC-LDPC) base graph.