US 12,395,188 B2
Apparatus and method for processing receive data in a receive data path including parallel FEC decoding
Sailaja Akkem, Austin, TX (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Oct. 5, 2023, as Appl. No. 18/481,359.
Claims priority of provisional application 63/378,690, filed on Oct. 7, 2022.
Prior Publication US 2024/0120944 A1, Apr. 11, 2024
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/1137 (2013.01) [H03M 13/6561 (2013.01)] 38 Claims
OG exemplary drawing
 
20. A method comprising:
converting an input data stream having an input bit width to a first output data stream having a first output bit width and to a second output data stream having a second output bit width, the input data stream and the first output data stream in a receive data path;
performing a forward error correction (FEC) decoding process on one or more FEC code words of the second output data stream having the second output bit width to produce one or more error correction values, at least a part of the FEC decoding process performed in parallel with the receive data path;
correcting one or more symbols, one or more partial symbols, or both, in the first output data stream having the first output bit width at least partially based on the one or more error correction values; and
signaling a latency predictor with a clock count value for selection of a latency value, the latency predictor comprising a look up table of latency values respectively associated with clock count values, the latency value for adjustment of timing used for timestamping data stream communications in the receive data path.