US 12,395,187 B2
Computer architecture with data decompression support for neural network computing
Chih-Chun Liu, Hsinchu (TW); Liang-Yu Chen, Hsinchu (TW); and Yao Ting Wang, Hsinchu (TW)
Assigned to MediaTek, Inc., Hsinchu (TW)
Filed by MediaTek Inc., Hsinchu (TW)
Filed on Aug. 18, 2023, as Appl. No. 18/451,925.
Prior Publication US 2025/0062778 A1, Feb. 20, 2025
Int. Cl. H03M 7/30 (2006.01); G06F 7/483 (2006.01); G06F 17/16 (2006.01)
CPC H03M 7/6005 (2013.01) [H03M 7/3082 (2013.01); G06F 7/483 (2013.01); G06F 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor operative to decompress a compressed data vector into an original data vector, comprising:
a mask register;
a general-purpose register file including a vector register; and
an execution circuit operative to:
receive a decompress instruction that includes two input operands indicating an address of the compressed data vector in a memory and an output operand indicating the vector register for storing the original data vector after decompression; and
execute the decompress instruction to decompress the compressed data vector, wherein the execution circuit when executing the decompress instruction is further operative to:
read a mask value from the mask register, the mask value being a binary sequence indicating zero positions in the original data vector;
generate a selection signal based on the mask value; and
generate the original data vector by applying the selection signal to a selection switch that receives the compressed data vector as input.