| CPC H03M 1/38 (2013.01) [H03M 1/1245 (2013.01)] | 20 Claims |
|
1. An analog-to-digital converter comprising:
a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses, the plurality of positive pulses respectively input to the plurality of stages and the plurality of negative pulses respectively input to the plurality of stages; and
a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuits configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.
|