| CPC H03M 1/0604 (2013.01) | 18 Claims |
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1. A successive approximation analog to digital conversion (SAADC) circuit having optimized linearity, comprising:
a control circuit;
at least one capacitor array comprising:
a lower-bit capacitor array comprising a plurality of lower-bit capacitors;
a higher-bit capacitor array comprising a plurality of unit capacitors each having a unit capacitance approximately equal to each other; and
a capacitor enabling circuit; and
a comparator electrically coupled between the capacitor array and the control circuit;
wherein in an initializing mode, the control circuit performs a sorting process on the unit capacitors according to the unit capacitances thereof to generate a sorting result to configure the unit capacitors to be a plurality of higher-bit capacitors according to the sorting result such that a linearity parameter of the higher-bit capacitors is within a predetermined range, wherein:
the sorting process performed on the unit capacitors by the control circuit comprises K sorting stages each correspondingly processing a plurality of items to be processed, in which K is an integer larger than or equal to 1, and the items to be processed corresponding to a first sorting stage are the unit capacitances of the unit capacitors;
in each of the K sorting stages, the control circuit performs a sorting operation and a combining operation on the items to be processed, in which the sorting operation sorts a total capacitance of the unit capacitors comprised by each of the items to be processed in ascending order or in descending order to generate a plurality of sorted items, and the combining operation combines a plurality pairs of the sorted items to generate a plurality of combined items, in which for each pair of the sorted items, one the sorted items is larger than or equal to a median of the sorted items and the other one of the sorted items is smaller than or equal to the median; and
the combined items generated in each of the first to K−1-th sorting stages serve as the items to be processed of a next one of the sorting stages, and the combined items generated in the K-th sorting stages serve as a plurality of items to be allocated; and
in an operation mode, the capacitor array receives an analog input signal and a plurality of reference voltage to generate an analog output signal, the comparator generates a comparison result at least according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit capacitors and the lower-bit capacitors to be coupled to one of the reference voltages by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.
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