US 12,395,178 B2
Partial-fractional phase-locked loop with sigma delta modulator and finite impulse response filter
Reetika K Agarwal, San Jose, CA (US); Abbas Komijani, Mountain View, CA (US); and Hongrui Wang, San Jose, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 9, 2023, as Appl. No. 18/447,221.
Application 18/447,221 is a division of application No. 17/835,292, filed on Jun. 8, 2022, granted, now 11,955,979.
Prior Publication US 2023/0403014 A1, Dec. 14, 2023
Int. Cl. H04L 5/00 (2006.01); H03C 3/09 (2006.01); H03L 7/089 (2006.01); H03L 7/091 (2006.01); H03L 7/099 (2006.01); H03L 7/185 (2006.01); H03L 7/197 (2006.01); H04L 7/033 (2006.01)
CPC H03L 7/0891 (2013.01) [H03C 3/0941 (2013.01); H03L 7/091 (2013.01); H03L 7/099 (2013.01); H03L 7/185 (2013.01); H03L 7/1976 (2013.01); H04L 7/033 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Wireless circuitry comprising:
a first mixer having an input configured to receive a first oscillator signal;
a second mixer coupled in series with the first mixer and having an input configured to receive a second oscillator signal;
a partial-fractional phase-locked loop circuit configured to generate the first oscillator signal; and
a phase-locked loop circuit of a different type than the partial-fractional phase-locked loop circuit, the phase-locked loop circuit being configured to generate the second oscillator signal.