US 12,395,176 B2
Multiple sample-rate data converter
Joshua J. O'Brien, Aloha, OR (US); Timothy E. Bieber, Portland, OR (US); and Barton T. Hickman, Portland, OR (US)
Assigned to Tektronix, Inc., Beaverton, OR (US)
Filed by Tektronix, Inc., Beaverton, OR (US)
Filed on Jun. 21, 2022, as Appl. No. 17/845,896.
Claims priority of provisional application 63/212,574, filed on Jun. 18, 2021.
Prior Publication US 2022/0407523 A1, Dec. 22, 2022
Int. Cl. H03L 7/07 (2006.01); H03L 7/14 (2006.01)
CPC H03L 7/07 (2013.01) [H03L 7/148 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A test and measurement instrument, comprising:
a user interface having an input selector structured to accept an indication of a test channel or channels from a user;
an input of the test and measurement instrument configured to receive a signal from a device under test, a portion of the signal including data from the one or more test channel inputs selected by the user for sampling;
a first data channel of the input including a first data converter configurable to operate at a first sampling rate;
a second data channel of the input including a second data converter configurable to operate at a second sampling rate that is different than the first sampling rate;
a clock generation circuit, including:
an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, an operational frequency of the intermediate frequency clock being different from an operational frequency of the first clock reference signal;
a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, the first frequency clock coupled to the first data converter to cause the first data channel to operate at the first sampling rate to sample and store the signal from the device under test as a first sampled waveform, and
a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock, the second frequency clock coupled to the second data converter to cause the second data channel to operate at the second sampling rate to sample and store the signal from the device under test as a second sampled waveform; and
an output configured to send an output signal to a display, the output signal including output derived from the first sampled waveform and the second sampled waveform.