US 12,395,174 B1
Clock-free serialization of asynchronous signals
Victor Zyuban, Sunnyvale, CA (US); Hemangi U. Gajjewar, Sunnyvale, CA (US); and Ajay Bhatia, Saratoga, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Dec. 8, 2023, as Appl. No. 18/534,500.
Claims priority of provisional application 63/581,233, filed on Sep. 7, 2023.
Int. Cl. H03K 5/00 (2006.01); H03K 3/037 (2006.01); H03K 5/01 (2006.01); H03K 19/00 (2006.01); H03K 19/21 (2006.01)
CPC H03K 19/0008 (2013.01) [H03K 3/037 (2013.01); H03K 5/01 (2013.01); H03K 19/21 (2013.01); H03K 2005/00013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a serializer circuit configured to:
receive a first asynchronous signal and a second asynchronous signal;
generate a first serialized signal by blocking transitions of the first asynchronous signal in response to a detection of a transition of the second asynchronous signal; and
generate a second serialized signal by blocking transitions of the second asynchronous signal in response to a detection of a transition of the first asynchronous signal; and
a digital circuit configured to:
generate a first output signal using the first serialized signal; and
generate a second output signal using the second serialized signal.