US 12,395,173 B2
Integrated circuit that applies different data interface terminations during and after write data reception
Kyung Suk Oh, Cupertino, CA (US); and Ian P. Shaeffer, Los Gatos, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on May 16, 2022, as Appl. No. 17/745,435.
Application 17/745,435 is a continuation of application No. 16/940,349, filed on Jul. 27, 2020, granted, now 11,349,478.
Application 16/940,349 is a continuation of application No. 16/853,658, filed on Apr. 20, 2020, granted, now 10,944,400, issued on Mar. 9, 2021.
Application 16/853,658 is a continuation of application No. 16/356,243, filed on Mar. 18, 2019, granted, now 10,651,849, issued on May 12, 2020.
Application 16/356,243 is a continuation of application No. 16/051,291, filed on Jul. 31, 2018, granted, now 10,270,442, issued on Apr. 23, 2019.
Application 16/051,291 is a continuation of application No. 15/581,480, filed on Apr. 28, 2017, granted, now 10,056,902, issued on Aug. 21, 2018.
Application 15/581,480 is a continuation of application No. 15/132,532, filed on Apr. 19, 2016, granted, now 9,660,648, issued on May 23, 2017.
Application 15/132,532 is a continuation of application No. 14/857,794, filed on Sep. 17, 2015, granted, now 9,337,835, issued on May 10, 2016.
Application 14/857,794 is a continuation of application No. 14/523,923, filed on Oct. 26, 2014, granted, now 9,166,583, issued on Oct. 20, 2015.
Application 14/523,923 is a continuation of application No. 13/952,393, filed on Jul. 26, 2013, granted, now 8,981,811, issued on Mar. 17, 2015.
Application 13/952,393 is a continuation of application No. 13/480,298, filed on May 24, 2012, granted, now 8,610,459, issued on Dec. 17, 2013.
Application 13/480,298 is a continuation of application No. 13/180,550, filed on Jul. 12, 2011, granted, now 8,188,762, issued on May 29, 2012.
Application 13/180,550 is a continuation of application No. 13/043,946, filed on Mar. 9, 2011, granted, now 8,089,298, issued on Jan. 3, 2012.
Application 13/043,946 is a continuation of application No. 12/861,771, filed on Aug. 23, 2010, granted, now 7,924,048, issued on Apr. 12, 2011.
Application 12/861,771 is a continuation of application No. 12/507,794, filed on Jul. 22, 2009, granted, now 7,782,082, issued on Aug. 24, 2010.
Application 12/507,794 is a continuation of application No. 12/199,726, filed on Aug. 27, 2008, granted, now 7,602,209, issued on Oct. 13, 2009.
Application 12/199,726 is a continuation of application No. 11/422,022, filed on Jun. 2, 2006, granted, now 7,486,104, issued on Feb. 3, 2009.
Prior Publication US 2022/0345131 A1, Oct. 27, 2022
Int. Cl. H03K 19/00 (2006.01); G06F 3/06 (2006.01); G06F 13/40 (2006.01); G11C 11/401 (2006.01); G11C 11/4063 (2006.01); G11C 11/4093 (2006.01); G11C 11/41 (2006.01); G11C 11/413 (2006.01); G11C 11/417 (2006.01); G11C 11/419 (2006.01); G11C 16/06 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); H03K 19/0175 (2006.01)
CPC H03K 19/0005 (2013.01) [G06F 3/0605 (2013.01); G06F 3/0659 (2013.01); G06F 3/0685 (2013.01); G06F 13/4086 (2013.01); G11C 11/401 (2013.01); G11C 11/4063 (2013.01); G11C 11/4093 (2013.01); G11C 11/41 (2013.01); G11C 11/413 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01); G11C 16/06 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); H03K 19/017545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit component comprising:
a data interface;
a command interface;
a chip-select input;
one or more programmable registers to store first and second termination control values; and
control circuitry to:
enable the command interface to receive a memory access command if a chip-select signal is asserted at the chip-select input during a first interval and, if the memory access command indicates a memory write operation, to:
transition a termination coupled to the data interface from a first impedance specified by the first control value to a second impedance specified by the second control value;
enable the data interface to receive write data during a write-data reception interval that transpires after the termination coupled to the data interface has transitioned to the second impedance; and
transition the termination coupled to the data interface from the second impedance to the first impedance after the write-data reception interval transpires; and
maintain the termination coupled to the data interface at the first impedance throughout a time period that would otherwise constitute the write-data reception interval if the chip-select signal is not asserted at the chip-select input during the first interval.