US 12,395,171 B2
Switch circuits with parallel transistor stacks and capacitor networks for balancing off-state RF voltages, and methods of their operation
Venkata Naga Koushik Malladi, Chandler, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Sep. 30, 2021, as Appl. No. 17/449,486.
Application 17/449,486 is a continuation in part of application No. 16/944,612, filed on Jul. 31, 2020, granted, now 11,368,180.
Prior Publication US 2022/0038098 A1, Feb. 3, 2022
Int. Cl. H03K 17/687 (2006.01); H04B 1/40 (2015.01)
CPC H03K 17/6871 (2013.01) [H04B 1/40 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A switch circuit comprising:
a first port;
a second port;
a first transistor stack coupled between the first and second ports, wherein the first transistor stack comprises a first group of multiple first transistors and at least one additional first transistor coupled between the first and second ports, wherein the multiple first transistors and the at least one additional first transistor all are connected together in series between drains and sources of transistors of the multiple first transistors and at the least one additional transistor to provide a first variably-conductive path between the first and second ports;
a first balancing capacitor having a fixed value with a first terminal directly coupled to an input of multiple transistors of the first group of multiple first transistors and a second terminal directly coupled to an output of the multiple transistors of the first group of multiple first transistors, wherein the first terminal and the second terminal of the first balancing capacitor are directly coupled across multiple transistors of the first group of multiple first transistors, and wherein the input of the first group of multiple first transistors is directly coupled to the first port; and
a second transistor stack coupled between the first and second ports, wherein the second transistor stack comprises a second group of multiple second transistors and at least one additional second transistor coupled between the first and second ports, wherein the multiple second transistors and the at least one additional second transistor all are connected together in series to provide a second variably-conductive path between the first and second ports; and
a second balancing capacitor network that includes one or more second capacitors, wherein a second capacitor of the one or more second capacitors is directly coupled across a second group of multiple transistors of the second plurality of transistors.