US 12,395,165 B2
Apparatus and methods to control well bias in a semiconductor device
Taewoo Kwak, McKinney, TX (US); Benjamin Amey, Allen, TX (US); and Daijiro Otani, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 31, 2023, as Appl. No. 18/385,852.
Prior Publication US 2025/0141443 A1, May 1, 2025
Int. Cl. H03K 17/10 (2006.01); H03K 17/687 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 17/102 (2013.01) [H03K 17/687 (2013.01); H03K 19/018514 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A circuit comprising:
a substrate including a first transistor of a gate driver output stage, the substrate including a first well region;
a diode circuit including a first terminal and a second terminal, the first terminal coupled to a first tap of the first well region; and
a second transistor including a first terminal, a second terminal, and a body, the first terminal of the second transistor coupled to a switching voltage terminal, and the second terminal and the body of the second transistor coupled to the first tap of the first well region and to the first terminal of the diode circuit.