| CPC H03K 3/356121 (2013.01) [G01R 31/318541 (2013.01); H03K 3/012 (2013.01); H03K 3/037 (2013.01)] | 20 Claims |
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1. A flip-flop (FF) comprising:
a first n-channel metal oxide semiconductor (NMOS) transistor connected to a ground line and operating based on an input signal;
a first p-channel metal oxide semiconductor (PMOS) transistor connected to a power voltage line and operating based on the input signal;
a second NMOS transistor connecting a first node to the first NMOS transistor and operating based on a pulse signal;
a second PMOS transistor connecting the first node to the first PMOS transistor and operating based on an inverted pulse signal inverted with respect to the pulse signal;
a third NMOS transistor and a fourth NMOS transistor, connected to the second NMOS transistor in parallel, and forming a first discharge path for connecting the first node to the ground line, based at least on a clock signal;
a third PMOS transistor and a fourth PMOS transistor, connected to the second PMOS transistor in parallel, and forming a first charge path for connecting the first node to the power voltage line, based at least on an inverted clock signal inverted with respect to the clock signal;
a keeper circuit connected to the first node to maintain a voltage level of the first node; and
an inverter generating an output signal by inverting a signal at the first node.
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