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1. A highly reliable positive-to-negative voltage conversion circuit, wherein the highly reliable positive-to-negative voltage conversion circuit comprises a first inverter, a first buffer, a second buffer, a first N-type metal-oxide-silicon (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first P-type metal-oxide-silicon (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein the first inverter, the first buffer and the second buffer each has an input terminal, an output terminal, a power terminal and a ground terminal; the input terminal of the first buffer is a signal input terminal of the positive-to-negative voltage conversion circuit; the power terminal of the first buffer, the power terminal of the first inverter, a source of the first PMOS transistor, a source of the second PMOS transistor and a source of the third PMOS transistor are connected at a connection terminal of a positive-voltage power supply terminal of the positive-to-negative voltage conversion circuit for connecting to a positive voltage; the ground terminal of the first buffer is grounded, and the output terminal of the first buffer is connected to the input terminal of the first inverter and a gate of the first PMOS transistor, respectively; the ground terminal of the first inverter is grounded, and the output terminal of the first inverter is connected to a gate of the second PMOS transistor; a drain of the first PMOS transistor is connected to a terminal of the first resistor, a drain of the second PMOS transistor is connected to a terminal of the second resistor, and the other terminal of the first resistor, a terminal of the third resistor, a drain of the first NMOS transistor and a gate of the second NMOS transistor are connected; the other terminal of the second resistor, a terminal of the fourth resistor, a drain of the second NMOS transistor, a gate of the first NMOS transistor and an input terminal of the second buffer are connected; the other terminal of the third resistor is connected to a drain of the third NMOS transistor; the other terminal of the fourth resistor is connected to a drain of the sixth NMOS transistor; a source of the first NMOS transistor is connected to a drain of the fourth NMOS transistor; a source of the second NMOS transistor is connected to a drain of the fifth NMOS transistor; a drain of the seventh NMOS transistor, a gate of the third NMOS transistor, a gate of the fourth NMOS transistor, a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected; a power terminal of the second buffer, a source of the third NMOS transistor, a source of the fourth NMOS transistor, a source of the fifth NMOS transistor and a source of the sixth NMOS transistor are connected at a connection terminal of a negative-voltage power supply terminal of the positive-to-negative voltage conversion circuit for connecting a negative voltage; a ground terminal of the second buffer is grounded; a gate of the third PMOS transistor, and a drain of the third PMOS transistor and a gate of the seventh NMOS transistor are connected; a source of the seventh NMOS transistor is grounded; and an output terminal of the second buffer is an output terminal of the positive-to-negative voltage conversion circuit.
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