US 12,395,158 B2
Multi-bit flip flop
Chi-Lin Liu, Taipei (TW); Shang-Chih Hsieh, Yangmei (TW); and Wei-Hsiang Ma, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/448,027.
Application 18/448,027 is a continuation of application No. 17/082,368, filed on Oct. 28, 2020, granted, now 11,824,538.
Claims priority of provisional application 62/954,987, filed on Dec. 30, 2019.
Prior Publication US 2024/0056061 A1, Feb. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/037 (2006.01); H03K 19/21 (2006.01)
CPC H03K 3/037 (2013.01) [H03K 19/21 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a multi-bit flip flop comprising a plurality of single bit flip flops;
an integrated clock gating circuit comprising an edge triggered flip flop having a data input terminal, an enable terminal, and an output terminal, wherein the data input terminal of the flip flop of the integrated clock gating circuit receives a clock pulse, and wherein the output terminal of the flip flop of the integrated clock gating circuit is connected directly to a clock input terminal of each single bit flip flop of the multi-bit flip flop; and
a control circuit, wherein the control circuit is operative to:
determine a plurality of output data comprising a logical disjunction of input data to a data input terminal of each single bit flip flop and output data at corresponding out terminal of the each single bit flip flop corresponding to the input data;
determine a logical disjunction of the plurality of output data;
generate an enable signal based on the logical disjunction of the plurality of output data, wherein the control circuit being operative to generate the enable signal based on the logical disjunction of the plurality of output data comprises the control circuit being operative to generate the enable signal having a first logic value when the output data corresponding to the input data of any of the plurality of single bit flip flops is different than the input data, and
provide the enable signal to the enable terminal of the flip flop of the integrated clock gating circuit; and
wherein the flip flop of the integrated clock gating circuit is operative to:
generate a clock signal from the clock pulse received at the data input terminal of the flip flop of the integrated clock gating circuit when the enable signal having the first logical value is received at the enable terminal of the flip flop of the integrated clock gating circuit, and
directly provide the clock signal to each single bit flip flop of the multi-bit flip flop causing the multi-bit flip flop to toggle.