US 12,395,157 B2
Footprint for multi-bit flip flop
Po-Chun Wang, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Chih-Liang Chen, Hsinchu (TW); Jerry Chang-Jui Kao, Taipei (TW); and Tzu-Ying Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Nov. 21, 2022, as Appl. No. 17/991,717.
Application 17/991,717 is a continuation of application No. 16/900,765, filed on Jun. 12, 2020, granted, now 11,509,293.
Prior Publication US 2023/0090614 A1, Mar. 23, 2023
Int. Cl. G01R 31/3187 (2006.01); H03K 3/037 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 89/10 (2025.01)
CPC H03K 3/037 (2013.01) [G01R 31/3187 (2013.01); H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a plurality of first bit cells each arranged in one of a plurality of first cell rows having a first row height;
a plurality of second bit cells each arranged in one of a plurality of second cells rows having a second row height different from the first row height, wherein the plurality of second bit cells extend to pass the plurality of first bit cells in a first direction; and
a plurality of clock cells arranged in peripheral regions of a multi-bit flip flop cell in the plurality of first cell rows,
wherein the plurality of first and second bit cells and the plurality of clock cells are included in the multi-bit flip flop cell,
wherein a first clock cell in the plurality of clock cells has a first boundary abutting a first cell in the plurality of first bit cells and a second boundary abutting a first cell in the plurality of second bit cells, the first boundary and the second boundary being perpendicular to each other.