US 12,395,093 B2
Integrated half-bridge power converter
Daniel M. Kinzer, El Segundo, CA (US); Jason Zhang, Monterey Park, CA (US); and Thomas Ribarich, Laguna Beach, CA (US)
Assigned to Navitas Semiconductor Limited, Dublin (DE)
Filed by Navitas Semiconductor Limited, Dublin (IE)
Filed on Jun. 21, 2023, as Appl. No. 18/339,123.
Application 18/339,123 is a continuation of application No. 17/169,320, filed on Feb. 5, 2021, granted, now 11,715,720.
Claims priority of provisional application 63/077,526, filed on Sep. 11, 2020.
Prior Publication US 2023/0387067 A1, Nov. 30, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 25/18 (2023.01); H02M 1/00 (2006.01); H02M 1/36 (2007.01); H02M 3/00 (2006.01); H02M 3/158 (2006.01); H02M 7/219 (2006.01); H10D 62/83 (2025.01); H10D 62/85 (2025.01)
CPC H02M 7/219 (2013.01) [H01L 23/4951 (2013.01); H01L 23/49575 (2013.01); H01L 25/18 (2013.01); H02M 1/0009 (2021.05); H02M 1/0048 (2021.05); H02M 1/36 (2013.01); H02M 3/003 (2021.05); H02M 3/158 (2013.01); H01L 2224/4807 (2013.01); H01L 2224/48229 (2013.01); H01L 2924/1425 (2013.01); H01L 2924/14252 (2013.01); H01L 2924/15333 (2013.01); H10D 62/83 (2025.01); H10D 62/8503 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an electronic device, the method comprising:
providing an electrically conductive package base including a high side die attach pad, a low side die attach pad and a plurality of I/O terminals;
attaching a low side gallium nitride (GaN) based die to the low side die attach pad, the low side GaN-based die including a low side gate, a low side drain, a low side source and a level shifter circuit;
providing a silicon-based die including:
an input for receiving a control signal;
an output for transmitting a gate control signal;
a gate voltage regulator circuit that regulates power of a driver circuit; and
a control circuit arranged to deliver a pulse width modulated (PWM) signal to the low side gate of the low side GaN-based die;
attaching a high side GaN-based die attached to the high side die attach pad, the high side GaN-based die including a high side source coupled to the low side drain, a high side gate coupled to the level shifter circuit, and a high side drain coupled to one or more of the plurality of I/O terminals; and
encapsulating at least partially, by an encapsulant, the package base, the low side GaN-based die, the silicon-based die, and the high side GaN-based die.