US 12,394,773 B2
Laser ablation-based surface property modification and contamination removal
Denis Myasishchev, Chandler, AZ (US); Andrew V. Mazur, Tempe, AZ (US); Purushotham Kaushik Muthur Srinath, Chandler, AZ (US); Robert M. Nickerson, Chandler, AZ (US); and Shripad Gokhale, Gilbert, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 28, 2023, as Appl. No. 18/399,178.
Application 18/399,178 is a continuation of application No. 16/557,771, filed on Aug. 30, 2019.
Prior Publication US 2024/0128253 A1, Apr. 18, 2024
Int. Cl. H01L 25/18 (2023.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/3142 (2013.01); H01L 23/315 (2013.01); H01L 25/0657 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An electronic system, comprising:
a bottom package comprising a first package substrate having a top side and an opposite bottom side, a first die coupled to the top side of the first package substrate by interconnects, a first mold layer over the first package substrate and in contact with the first die, the first mold layer having an uppermost surface above an uppermost surface of the first die, and through mold interconnects through the first mold layer and laterally adjacent to the first die;
a top package coupled to the bottom package, the top package comprising a second package substrate having a top side and an opposite bottom side, a second die above and coupled to the top side of the second package substrate by a first wire bond, and a third die above the second die, the third die coupled to the top side of the second package substrate by a second wire bond, a second mold layer over the second die and the third die and over the second package substrate, and a solder resist layer on the bottom side of the second package substrate, wherein the solder resist has a cavity therein, the cavity having a depth less than a thickness of the solder resist, wherein the second mold layer of the top package has a sidewall in vertical alignment with a sidewall of the first mold layer of the bottom package;
interconnects coupled to the bottom side of the first package substrate; and
a board coupled to the interconnects.