US 12,394,771 B2
Semiconductor die assemblies with sidewall protection and associated methods and systems
Yu Lin Kao, Taichung (TW); Chun Min Lin, Taichung (TW); Sui Chi Huang, Taichung (TW); and Pei Sian Shao, Taichung (TW)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 9, 2022, as Appl. No. 17/668,306.
Claims priority of provisional application 63/304,208, filed on Jan. 28, 2022.
Claims priority of provisional application 63/238,101, filed on Aug. 27, 2021.
Prior Publication US 2023/0068435 A1, Mar. 2, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/481 (2013.01); H01L 25/50 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor die assembly, comprising:
a first semiconductor die including a substrate having a first side in contact with a dielectric layer having a low-k dielectric material and conductive components coupled to integrated circuitry of the substrate;
one or more second semiconductor dies attached to a second side of the substrate opposite to the first side, the one or more second semiconductor dies operatively coupled to the integrated circuitry;
a monolithic encapsulating mold material surrounding the first semiconductor die and the one or more second semiconductor dies, the monolithic encapsulating mold material directly contacting first sidewalls of the substrate, second sidewalls of the dielectric layer, and third sidewalls of the one or more second semiconductor dies; and
a passivation layer in contact with the dielectric layer, wherein the passivation layer is opposite to the substrate of the first semiconductor die,
wherein the dielectric layer includes a ledge uncovered by the substrate, the ledge being in contact with the monolithic encapsulating mold material.