US 12,394,768 B2
Package structure
Jia-Tay Kuo, Hsinchu (TW); Chiao Fu, Hsinchu (TW); Sheng-Bo Wang, Hsinchu (TW); Chen-Yu Wang, Hsinchu (TW); and Yao-Zhong Liu, Hsinchu (TW)
Assigned to GaNrich Semiconductor Corporation, Hsinchu (TW)
Filed by GaNrich Semiconductor Corporation, Hsinchu (TW)
Filed on Feb. 24, 2023, as Appl. No. 18/113,774.
Claims priority of provisional application 63/313,869, filed on Feb. 25, 2022.
Prior Publication US 2023/0275073 A1, Aug. 31, 2023
Int. Cl. H01L 25/16 (2023.01); H01L 23/00 (2006.01); H03K 17/08 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/16 (2013.01) [H01L 24/48 (2013.01); H03K 17/08 (2013.01); H01L 23/49827 (2013.01); H01L 24/49 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/49111 (2013.01); H01L 2924/12035 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/19105 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a substrate;
a first carrier, a second carrier, and a third carrier, each disposed on the substrate
an integrated transistor, disposed on the substrate, wherein the integrated transistor comprises:
a transistor, comprising a gate, a drain, and a source, wherein the drain is electrically connected to the second carrier, and the gate is electrically connected to the third carrier;
a capacitor, electrically connected to the gate;
a resistor, electrically connected to the gate;
a first Zener diode, comprising a first anode and a first cathode, wherein the first cathode is electrically connected to the gate; and
a second Zener diode, comprising a second anode and a second cathode, wherein the second anode is electrically connected to the first anode, and the second cathode is electrically connected to the source through the first carrier; and
an encapsulation structure, encapsulating the integrated transistor;
wherein the package structure comprises a gate terminal, a drain terminal, and a source terminal.