US 12,394,759 B2
Semiconductor device and circuit device
Yasutaka Nakashiba, Tokyo (JP); Hiroshi Yanagigawa, Tokyo (JP); Kazuhisa Mori, Tokyo (JP); and Toshiyuki Hata, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Nov. 29, 2022, as Appl. No. 18/059,646.
Claims priority of application No. 2022-015407 (JP), filed on Feb. 3, 2022.
Prior Publication US 2023/0246002 A1, Aug. 3, 2023
Int. Cl. H01L 25/07 (2006.01); H01L 23/00 (2006.01); H10D 30/66 (2025.01); H10D 84/00 (2025.01); H02M 7/537 (2006.01)
CPC H01L 25/074 (2013.01) [H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 24/73 (2013.01); H10D 30/668 (2025.01); H10D 84/144 (2025.01); H01L 2224/32145 (2013.01); H01L 2224/40227 (2013.01); H01L 2224/73263 (2013.01); H01L 2924/13091 (2013.01); H02M 7/537 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode formed in the first MOSFET; and
a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode formed in the second MOSFET,
wherein a first source electrode and a first gate wiring are formed in a front surface of the first semiconductor chip,
wherein a first drain electrode is formed in a back surface of the first semiconductor chip,
wherein a first anode of the first parasitic diode is coupled to the first source electrode, and a first cathode of the first parasitic diode is coupled to the first drain electrode,
wherein a second source electrode and a second gate wiring are formed in a front surface of the second semiconductor chip,
wherein a second drain electrode is formed in a back surface of the second semiconductor chip,
wherein a second anode of the second parasitic diode is coupled to the second source electrode, and a second cathode of the second parasitic diode is coupled to the second drain electrode,
wherein the front surface of the first semiconductor chip and the front surface of the second semiconductor chip face each other such that the first source electrode and the second source electrode come in contact with each other via a first conductive member,
wherein the second semiconductor chip further includes a control circuit electrically connected to the first gate wiring and the second gate wiring, and
wherein the control circuit has a function of supplying a gate potential to each of the first gate wiring and the second gate wiring in order to switch an ON/OFF state of each of the first MOSFET and the second MOSFET.