US 12,394,757 B2
Semiconductor devices with redistribution structures configured for switchable routing
Travis M. Jensen, Boise, ID (US); and David R. Hembree, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 13, 2023, as Appl. No. 18/486,950.
Application 18/486,950 is a continuation of application No. 17/521,173, filed on Nov. 8, 2021, granted, now 11,791,316.
Application 17/521,173 is a continuation of application No. 16/836,283, filed on Mar. 31, 2020, granted, now 11,171,121, issued on Nov. 9, 2021.
Prior Publication US 2024/0055411 A1, Feb. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 25/50 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, the method comprising:
forming a first redistribution structure on a first semiconductor die;
forming a second redistribution structure on a second semiconductor die; and
selecting, based on a design of the semiconductor package, either a first position or a second position for an interconnect structure between the first and second semiconductor dies, wherein:
the first position corresponds to the interconnect structure electrically coupling a contact of the second die through the first and second redistribution structures to a first package contact of the semiconductor package, and
the second position corresponds to the interconnect structure electrically coupling the contact of the second die through the first and second redistribution structures to a second package contact of the semiconductor package; and
electrically coupling the first and second semiconductor dies with the interconnect structure in the selected first or second position.