US 12,394,756 B2
Backside integrated voltage regulator for integrated circuits
Namhoon Kim, San Jose, CA (US); Woon-Seong Kwon, Santa Clara, CA (US); Houle Gan, Santa Clara, CA (US); Yujeong Shim, Cupertino, CA (US); Mikhail Popovich, Danville, CA (US); and Teckgyu Kang, Saratoga, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Aug. 29, 2023, as Appl. No. 18/239,368.
Application 18/239,368 is a division of application No. 17/667,104, filed on Feb. 8, 2022, granted, now 11,830,855.
Application 17/667,104 is a continuation of application No. 16/788,994, filed on Feb. 12, 2020, granted, now 11,276,668, issued on Mar. 15, 2022.
Prior Publication US 2023/0402430 A1, Dec. 14, 2023
Int. Cl. H01L 25/065 (2023.01); H10D 1/20 (2025.01); H10D 1/68 (2025.01)
CPC H01L 25/0657 (2013.01) [H10D 1/20 (2025.01); H10D 1/68 (2025.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package comprising:
an application specific integrated circuit (ASIC) die including a silicon layer; and
an integrated power regulator die connected to the silicon layer by a power distribution network (PDN), wherein the IC package further includes a packaging substrate, wherein the integrated power regulator die is connected to the packaging substrate via one or more through mold vias (TMVs) or one or more dielectric vias (TDVs), wherein the integrated power regulator die is configured to receive power through the one or more TMVs or TDVs.