US 12,394,750 B2
Semiconductor assemblies with redistribution structures for die stack signal routing
Owen R. Fay, Meridian, ID (US); Madison E. Wale, Boise, ID (US); James L. Voelz, Boise, ID (US); Dylan W. Southern, Meridian, ID (US); and Dustin L. Holloway, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 20, 2024, as Appl. No. 18/668,777.
Application 18/668,777 is a continuation of application No. 18/094,320, filed on Jan. 6, 2023, granted, now 11,990,446.
Application 18/094,320 is a continuation of application No. 17/100,610, filed on Nov. 20, 2020, granted, now 11,552,045, issued on Jan. 10, 2023.
Claims priority of provisional application 63/066,436, filed on Aug. 17, 2020.
Prior Publication US 2024/0321822 A1, Sep. 26, 2024
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/82 (2013.01) [H01L 24/20 (2013.01); H01L 24/29 (2013.01); H01L 24/45 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 2224/82203 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor assembly comprising:
a package substrate;
a die stack mounted on the package substrate, the die stack including a plurality of semiconductor dies;
a routing substrate mounted on the die stack, the routing substrate including an upper surface facing away from the die stack;
a redistribution structure formed above the upper surface of the routing substrate; and
an electrical connector coupling the redistribution structure to the die stack, wherein the die stack is electrically coupled to the package substrate via the redistribution structure and the electrical connector without a direct electrical connection between a lowermost die of the die stack and the package substrate.