US 12,394,742 B2
Interconnect structure for high power GaN module including a printed planar interconnect line and method for making the same
Jie Chen, Plano, TX (US); Yong Xie, Plano, TX (US); Rajen Manicon Murugan, Dallas, TX (US); and Woochan Kim, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 22, 2020, as Appl. No. 17/028,353.
Claims priority of provisional application 62/945,672, filed on Dec. 9, 2019.
Prior Publication US 2021/0175195 A1, Jun. 10, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 23/66 (2006.01); H01L 25/16 (2023.01)
CPC H01L 24/24 (2013.01) [H01L 24/73 (2013.01); H01L 24/82 (2013.01); H01L 24/92 (2013.01); H01L 25/16 (2013.01); H01L 23/66 (2013.01); H01L 2223/6666 (2013.01); H01L 2224/24101 (2013.01); H01L 2224/24175 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82102 (2013.01); H01L 2224/82104 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1426 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A circuit module comprising:
a multilayer substrate having a first surface and an opposite second surface;
a first conductive pad formed within a first one of the layers of the multilayer substrate;
an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semiconductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; and
a first printed ink planar interconnect line coupled to a subset of the set of bond pads and to the conductive pad.