US 12,394,739 B2
Semiconductor package and method of manufacturing semiconductor package
Luguang Wang, Hefei (CN); and Jinrong Huang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Jun. 22, 2022, as Appl. No. 17/846,114.
Application 17/846,114 is a division of application No. PCT/CN2022/077782, filed on Feb. 24, 2022.
Claims priority of application No. 202210033878.X (CN), filed on Jan. 12, 2022.
Prior Publication US 2023/0223371 A1, Jul. 13, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/16 (2013.01) [H01L 24/81 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81895 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first base with a first surface, wherein a conductive pillar is arranged in the first base, the first surface comprises a first groove, and the first groove exposes a top surface and a portion of a sidewall of the conductive pillar;
a second base with a second surface, wherein the first surface is bonded to the second surface, the second surface comprises a second groove, an electrical connection pillar is arranged in the second base, the second groove is completely filled with the electrical connection pillar, and the electrical connection pillar protrudes from the second surface; and
an electrical connection structure, wherein the electrical connection structure and a portion of the electrical connection pillar are embedded into the first groove, and the electrical connection structure surrounds a portion of the conductive pillar exposed from the first groove and the portion of the electrical connection pillar embedded into the first groove.