US 12,394,731 B2
Compression structures for IC packages
Helia Rahmani, Mountain View, CA (US); Stephane J. Marcadet, San Mateo, CA (US); Scott J. Campbell, Sunnyvale, CA (US); Zhiyong C. Xia, San Jose, CA (US); Stephen V. Jayanathan, Seattle, WA (US); Vineet Negi, Sunnyvale, CA (US); and Christian Kettenbeil, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 23, 2022, as Appl. No. 17/951,978.
Prior Publication US 2024/0105639 A1, Mar. 28, 2024
Int. Cl. H05K 1/02 (2006.01); H01L 23/00 (2006.01); H01L 23/053 (2006.01); H05K 1/18 (2006.01); H05K 5/00 (2006.01); H05K 5/10 (2025.01)
CPC H01L 23/562 (2013.01) [H01L 23/053 (2013.01); H05K 1/181 (2013.01); H05K 5/0091 (2013.01); H05K 5/10 (2025.01); H05K 2201/10378 (2013.01); H05K 2201/10393 (2013.01); H05K 2201/10409 (2013.01); H05K 2201/10598 (2013.01); H05K 2201/10734 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising: a board; a component attached to a first side of the board; an edge bond between a corner of the component and the first side of the board; a first housing portion; and a first compressible support between the component and the first housing portion.