US 12,394,728 B2
Method of forming a region shielding within a package of a microelectronic device
Patrick Variot, Los Gatos, CA (US); and Hong Shen, Palo Alto, CA (US)
Assigned to Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed on May 23, 2024, as Appl. No. 18/673,099.
Application 18/673,099 is a division of application No. 17/509,887, filed on Oct. 25, 2021, granted, now 12,021,041.
Claims priority of provisional application 63/108,096, filed on Oct. 30, 2020.
Prior Publication US 2024/0312928 A1, Sep. 19, 2024
Int. Cl. H01L 23/552 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 23/31 (2013.01); H01L 23/5226 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method comprising:
providing a substrate comprising plurality of pillars and one of (i) a conductive trace or (ii) a plurality of conductive pads, wherein a first end of individual pillars of the plurality of pillars is coupled to one of (i) the conductive trace or (ii) a corresponding conductive pad of a plurality of conductive pads;
attaching a first chip to the substrate adjacent to a first side of the plurality of pillars;
attaching a second chip to the substrate adjacent to a second side of the plurality of pillars, wherein the second side is opposite to the first side;
disposing an epoxy molding compound over at least the first chip, the second chip, and the plurality of pillars to provide a cover;
forming a trench in the cover; and
filling the trench with a conductive material, wherein:
a second end of each pillar of the plurality of pillars is at least adjacent to the trench defined within the cover,
a spacing among the plurality of pillars is at least equal to a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the first chip and the second chip,
the individual pillars of the plurality of pillars are arranged in a preselected manner for one or more frequencies associated with an interference between the first chip and the second chip; and
the plurality of pillars are positioned to substantially shield the interference at the one or more frequencies between the first chip and the second chip.