US 12,394,722 B2
Dielectric capacitance recovery of inter-layer dielectric layers for advanced integrated circuit structure fabrication
Atul Madhavan, Portland, OR (US); Abhishek Jain, Portland, OR (US); Jinhong Shin, Portland, OR (US); and Anant H. Jahagirdar, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/131,701.
Claims priority of provisional application 63/083,737, filed on Sep. 25, 2020.
Prior Publication US 2022/0102279 A1, Mar. 31, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/52 (2006.01); H01L 23/538 (2006.01); H01L 29/40 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/76802 (2013.01); H01L 23/49877 (2013.01); H01L 23/5386 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a single dielectric layer above a substrate, wherein the single dielectric layer is structurally continuous from a bottommost surface of the single dielectric layer to an uppermost surface of the single dielectric layer;
a plurality of conductive lines in an upper portion of the single dielectric layer above a lower portion of the single dielectric layer; and
a carbon dopant region in the upper portion of the single dielectric layer, the carbon dopant region between adjacent ones of the plurality of conductive lines, and the carbon dopant region having an uppermost surface at a same level as an uppermost surface of the plurality of conductive lines.