US 12,394,716 B2
Integrated circuit interconnect structures with graphene cap
Carl Naylor, Portland, OR (US); Jasmeet Chawla, Hillsboro, OR (US); Matthew Metz, Portland, OR (US); Sean King, Beaverton, OR (US); Ramanan Chebiam, Hillsboro, OR (US); Mauro Kobrinsky, Portland, OR (US); Scott Clendenning, Portland, OR (US); Sudarat Lee, Hillsboro, OR (US); Christopher Jezewski, Portland, OR (US); Sunny Chugh, Hillsboro, OR (US); and Jeffery Bielefeld, Forest Grove, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,962.
Prior Publication US 2022/0415818 A1, Dec. 29, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/3215 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/3215 (2013.01); H01L 21/7685 (2013.01); H01L 23/53266 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a plurality of transistors; and
an interconnect structure coupled to at least one of the transistors, wherein the interconnect structure comprises:
a first metal; and
graphene over, and in direct contact with, a top surface of the first metal, wherein the graphene comprises a plurality of grains spaced apart from adjacent grains,
wherein an amount of a second metal, nitrogen or silicon within the first metal is higher proximal to an interface of the graphene than distal from the interface, and higher within a first region of the first metal below spaces between the grains than within a second region of the first metal immediately below individual ones of the grains.